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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 8: External Memory Interfaces in the Cyclone III Device Family  
8–13  
Cyclone III Device Family Memory Interfaces Features  
f
For more information about Cyclone III device family IOE registers, refer to the  
I/O Features in the Cyclone III Device Family chapter.  
Figure 8–6 shows how the second output enable register extends the DQS  
high-impedance state by half a clock cycle during a write operation.  
(1)  
Figure 8–6. Extending the OE Disable by Half a Clock Cycle for a Write Transaction  
System clock  
(outclock for DQS)  
OE for DQS  
Delay  
90o  
(from logic array)  
by Half  
a Clock  
Cycle  
Preamble  
Postamble  
DQS  
Write Clock  
(outclock for DQ,  
o
-90 phase shifted  
from System Clock)  
datain_h  
(from logic array)  
D0  
D2  
D3  
datain_I  
(from logic array)  
D1  
OE for DQ  
(from logic array)  
DQ  
D0  
D1  
D2  
D3  
Note to Figure 8–6:  
(1) The waveform reflects the software simulation result. The OEsignal is an active low on the device. However, the Quartus II software implements  
the signal as an active high and automatically adds an inverter before the AOE register D input.  
OCT  
Cyclone III device family supports calibrated on-chip series termination (RS OCT) in  
both vertical and horizontal I/O banks. To use the calibrated OCT, you must use the  
RUP and RDN pins for each RS OCT control block (one for each side). You can use  
each OCT calibration block to calibrate one type of termination with the same VCCIO  
for that given side.  
f
For more information about Cyclone III device family OCT calibration block, refer to  
the Cyclone III Device I/O Features chapter.  
PLL  
When interfacing with external memory, the PLL is used to generate the memory  
system clock, the write clock, the capture clock and the logic-core clock. The system  
clock generates the DQSwrite signals, commands, and addresses. The write-clock is  
shifted by -90° from the system clock and generates the DQsignals during writes. You  
can use the PLL reconfiguration feature to calibrate the read-capture phase shift to  
balance the setup and hold margins.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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