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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family  
7–3  
High-Speed I/O Interface  
Table 7–1 lists which I/O bank supports these I/O standards in the Cyclone III device  
family.  
Table 7–1. Differential I/O Standards Supported in Cyclone III Device Family I/O Banks  
External Resistor  
Network at  
Differential I/O Standards  
I/O Bank Location  
Transmitter (TX) Receiver (RX)  
Transmitter  
1,2,5,6  
All  
Not Required  
Three Resistors  
Not Required  
LVDS  
Yes  
Yes  
Yes  
Yes  
1,2,5,6  
3, 4, 7, 8  
All  
Not  
Supported  
RSDS  
Three Resistors  
Single Resistor  
Not Required  
1,2,5,6  
All  
Not  
Supported  
mini-LVDS  
PPDS  
Three Resistors  
Not Required  
1,2,5,6  
All  
Not  
Supported  
Yes  
Yes  
Three Resistors  
Single Resistor  
(1)  
BLVDS  
All  
Yes  
Yes  
Not  
Supported  
(2)  
LVPECL  
All  
NA  
(3)  
Differential SSTL-2  
All  
All  
All  
All  
All  
NA  
NA  
NA  
NA  
NA  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
(3)  
(3)  
(3)  
(3)  
Differential SSTL-18  
Differential HSTL-18  
Differential HSTL-15  
Differential HSTL-12  
Notes to Table 7–1:  
(1) Transmitter and Receiver FMAX depend on system topology and performance requirement.  
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.  
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock  
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.  
You can use I/O pins and internal logic to implement a high-speed differential  
interface in the Cyclone III device family. The Cyclone III device family does not  
contain dedicated serialization or deserialization circuitry. Therefore, shift registers,  
internal phase-locked loops (PLLs), and I/O cells are used to perform  
serial-to-parallel conversions on incoming data and parallel-to-serial conversion on  
outgoing data. The differential interface data serializers and deserializers (SERDES)  
are automatically constructed in the core logic elements (LEs) with the Quartus® II  
software ALTLVDS megafunction.  
December 2011 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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