Chapter 6: I/O Features in the Cyclone III Device Family
6–13
Termination Scheme for I/O Standards
Table 6–4. Cyclone III Device Family Supported I/O Standards and Constraints (Part 2 of 2)
Left and Right
I/O Pins
V
CCIO Level (in V)
Top and Bottom I/O Pins
Standard
Support
I/O Standard
Type
User
CLK,
CLK, UserI/O
Input
Output
PLL_OUT
I/O
Pins
DQS
DQS
Pins
(8)
LVDS
Differential
Differential
—
—
2.5
—
2.5
2.5
v
v
v
v
v
v
v
RSDS and
mini-LVDS
—
—
v
(4)
(6)
BLVDS
Differential
Differential
—
—
2.5
2.5
2.5
—
—
—
—
v
—
v
(5)
LVPECL
v
—
v
—
Notes to Table 6–4:
(1) The PCI-clamp diode must be enabled for 3.3-V/3.0-V LVTTL/LVCMOS.
(2) The Cyclone III architecture supports the MultiVolt I/O interface feature that allows Cyclone III devices to interface with I/O systems that have
different supply voltages.
(3) Differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as inverted. Differential HSTL and SSTL
inputs treat differential inputs as two single-ended HSTL and SSTL inputs and only decode one of them. Differential HSTL and SSTL are only
supported on CLKpins.
(4) PPDS, mini-LVDS, and RSDS are only supported on output pins.
(5) LVPECL is only supported on clock inputs.
(6) Bus LVDS (BLVDS) output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses LVDS input buffer.
(7) Class I and Class II refer to output termination and do not apply to input. 1.2-V HSTL input is supported at both column and row I/O regardless of
class.
(8) True differential LVDS, RSDS, and mini-LVDS I/O standards are supported in left and right I/O pins while emulated differential LVDS (LVDS_E_3R),
RSDS (RSDS_E_3R), and mini-LVDS (LVDS_E_3R) I/O standards are supported in both left and right, and top and bottom I/O pins.
The Cyclone III device family supports PCI and PCI-X I/O standards at 3.0-V VCCIO
.
The 3.0-V PCI and PCI-X I/O are fully compatible for direct interfacing with 3.3-V PCI
systems without requiring any additional components. The 3.0-V PCI and PCI-X
outputs meet the VIH and VIL requirements of 3.3-V PCI and PCI-X inputs with
sufficient noise margin.
f
For more information about the 3.3/3.0/2.5-V LVTTL and LVCMOS multivolt I/O
support, refer to AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5-V
LVTTL/LVCMOS I/O Systems.
Termination Scheme for I/O Standards
This section describes recommended termination schemes for voltage-referenced and
differential I/O standards.
The 3.3-V LVTTL, 3.0-V LVTTL and LVCMOS, 2.5-V LVTTL and LVCMOS,
1.8-V LVTTL and LVCMOS, 1.5-V LVCMOS, 1.2-V LVCMOS, 3.0-V PCI, and PCI-X
I/O standards do not specify a recommended termination scheme per the JEDEC
standard.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
