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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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6–2  
Chapter 6: I/O Features in the Cyclone III Device Family  
I/O Element Features  
Figure 6–1 shows the Cyclone III device family IOE structure.  
Figure 6–1. Cyclone III Device Family IOE in a Bidirectional I/O Configuration  
io_clk[5..0]  
Column  
or Row  
Interconnect  
OE  
OE Register  
V
CCIO  
D
Q
Optional  
PCI Clamp  
clkout  
ENA  
ACLR  
/PRN  
V
CCIO  
oe_out  
Programmable  
Pull-Up  
aclr/prn  
Resistor  
Chip-Wide Reset  
Output  
Pin Delay  
Output Register  
D
Q
Current Strength Control  
Open-Drain Out  
Slew Rate Control  
ENA  
ACLR  
sclr/  
preset  
/PRN  
data_in1  
data_in0  
Bus Hold  
Input Pin to  
Input Register  
Delay  
or Input Pin to  
Logic Array  
Delay  
D
Q
clkin  
ENA  
ACLR  
/PRN  
oe_in  
Input Register  
I/O Element Features  
The Cyclone III device family IOE offers a range of programmable features for an I/O  
pin. These features increase the flexibility of I/O utilization and provide an  
alternative to reduce the usage of external discrete components to on-chip, such as a  
pull-up resistor and a diode.  
Programmable Current Strength  
The output buffer for each Cyclone III device family I/O pin has a programmable  
current strength control for certain I/O standards.  
The LVTTL, LVCMOS, SSTL-2 Class I and Class II, SSTL-18 Class I and Class II,  
HSTL-18 Class I and Class II, HSTL-15 Class I and Class II, and HSTL-12 Class I  
and Class II I/O standards have several levels of current strength that you can  
control.  
Cyclone III Device Handbook  
Volume 1  
July 2012 Altera Corporation  
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