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DIFFCLK_6P 参数 Datasheet PDF下载

DIFFCLK_6P图片预览
型号: DIFFCLK_6P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–20  
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
Hardware Features  
Manual Override  
If you are using the automatic switchover, you must switch input clocks with the  
manual override feature with the clkswitchinput.  
Figure 5–16 shows an example of a waveform illustrating the switchover feature  
when controlled by clkswitch. In this case, both clock sources are functional and  
inclk0is selected as the reference clock. A low-to-high transition of the clkswitch  
signal starts the switchover sequence. The clkswitchsignal must be high for at least  
three clock cycles (at least three of the longer clock period if inclk0and inclk1have  
different frequencies). On the falling edge of inclk0, the reference clock of the counter,  
muxout, is gated off to prevent any clock glitching. On the falling edge of inclk1, the  
reference clock multiplexer switches from inclk0to inclk1as the PLL reference. On  
the falling edge of inclk1, the reference clock multiplexer switches from inclk0to  
inclk1as the PLL reference, and the activeclocksignal changes to indicate which  
clock is currently feeding the PLL.  
In this mode, the activeclocksignal mirrors the clkswitchsignal. As both blocks are  
still functional during the manual switch, neither clkbadsignals go high. Because the  
switchover circuit is positive edge-sensitive, the falling edge of the clkswitchsignal  
does not cause the circuit to switch back from inclk1to inclk0. When the clkswitch  
signal goes high again, the process repeats. The clkswitchsignal and the automatic  
switch only works depending on the availability of the clock that is switched to. If the  
clock is unavailable, the state machine waits until the clock is available.  
1
If CLKSWITCH = 1, the automatic switchover function is overridden. While the  
clkswitchsignal is high, further switchover action is blocked.  
(1)  
Figure 5–16. Clock Switchover Using the clkswitch Control  
inclk0  
inclk1  
muxout  
clkswitch  
activeclock  
clkbad0  
clkbad1  
Note to Figure 5–16:  
(1) Both inclk0and inclk1must be running when the clkswitchsignal goes high to start a manual clock switchover  
event.  
Cyclone III Device Handbook  
Volume 1  
July 2012 Altera Corporation