Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
2–7
Document Revision History
Figure 2–6 shows the LAB control signal generation circuit.
Figure 2–6. Cyclone III Device Family LAB-Wide Control Signals
Dedicated
6
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena2
labclkena1
labclr1
synclr
labclk1
labclk2
syncload
labclr2
LAB-wide signals control the logic for the clear signal of the register. The LE directly
supports an asynchronous clear function. Each LAB supports up to two asynchronous
clear signals (labclr1and labclr2).
A LAB-wide asynchronous load signal to control the logic for the preset signal of the
register is not available. The register preset is achieved with a NOT gate push-back
technique. The Cyclone III device family only supports either a preset or
asynchronous clear signal.
In addition to the clear port, the Cyclone III device family provides a chip-wide reset
pin (DEV_CLRn) that resets all registers in the device. An option set before compilation
in the Quartus II software controls this pin. This chip-wide reset overrides all other
control signals.
Document Revision History
Table 2–1 lists the revision history for this document.
Table 2–1. Document Revision History (Part 1 of 2)
Date
Version
2.3
Changes
December 2011
December 2009
July 2009
Minor text edits.
2.2
Minor changes to the text.
Minor edit to the hyperlinks.
2.1
Updated to include Cyclone III LS information
■ Updated chapter part number.
June 2009
2.0
1.2
■ Updated “Introduction” on page 2–1.
■ Updated Figure 2–1 on page 2–2 and Figure 2–4 on page 2–5.
■ Updated “LAB Control Signals” on page 2–6.
Updated chapter to new template.
October 2008
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
