欢迎访问ic37.com |
会员登录 免费注册
发布采购

DIFFCLK_6P 参数 Datasheet PDF下载

DIFFCLK_6P图片预览
型号: DIFFCLK_6P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号DIFFCLK_6P的Datasheet PDF文件第24页浏览型号DIFFCLK_6P的Datasheet PDF文件第25页浏览型号DIFFCLK_6P的Datasheet PDF文件第26页浏览型号DIFFCLK_6P的Datasheet PDF文件第27页浏览型号DIFFCLK_6P的Datasheet PDF文件第29页浏览型号DIFFCLK_6P的Datasheet PDF文件第30页浏览型号DIFFCLK_6P的Datasheet PDF文件第31页浏览型号DIFFCLK_6P的Datasheet PDF文件第32页  
2–2  
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family  
Logic Elements  
Figure 2–1 shows the LEs for the Cyclone III device family.  
Figure 2–1. Cyclone III Device Family LEs  
Register Chain  
Routing from  
previous LE  
Register Bypass  
LAB-Wide  
Synchronous LAB-Wide  
Programmable  
Register  
Load  
Synchronous  
Clear  
LE Carry-In  
data 1  
data 2  
Row, Column,  
And Direct Link  
Routing  
Synchronous  
Load and  
Clear Logic  
Carry  
Chain  
Look-Up Table  
data 3  
D
Q
(LUT)  
data 4  
ENA  
CLRN  
Row, Column,  
And Direct Link  
Routing  
labclr1  
labclr2  
Asynchronous  
Clear Logic  
Chip-Wide  
Reset  
Local  
Routing  
Register Feedback  
(DEV_CLRn)  
Clock &  
Clock Enable  
Select  
Register Chain  
Output  
labclk1  
LE Carry-Out  
labclk2  
labclkena1  
labclkena2  
LE Features  
You can configure the programmable register of each LE for D, T, JK, or SR flipflop  
operation. Each register has data, clock, clock enable, and clear inputs. Signals that  
use the global clock network, general-purpose I/O pins, or any internal logic can  
drive the clock and clear control signals of the register. Either general-purpose I/O  
pins or the internal logic can drive the clock enable. For combinational functions, the  
LUT output bypasses the register and drives directly to the LE outputs.  
Each LE has three outputs that drive the local, row, and column routing resources. The  
LUT or register output independently drives these three outputs. Two LE outputs  
drive the column or row and direct link routing connections, while one LE drives the  
local interconnect resources. This allows the LUT to drive one output while the  
register drives another output. This feature, called register packing, improves device  
utilization because the device can use the register and the LUT for unrelated  
functions. The LAB-wide synchronous load control signal is not available when using  
register packing. For more information on the synchronous load control signal, refer  
to “LAB Control Signals” on page 2–6.  
The register feedback mode allows the register output to feed back into the LUT of the  
same LE to ensure that the register is packed with its own fan-out LUT, providing  
another mechanism for improved fitting. The LE can also drive out registered and  
unregistered versions of the LUT output.  
Cyclone III Device Handbook  
Volume 1  
December 2011 Altera Corporation