Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
12–3
IEEE Std. 1149.1 BST Operation Control
Cyclone III device family supports the IEEE Std. 1149.1 (JTAG) instructions as listed in
Table 12–3.
Table 12–3. IEEE Std. 1149.1 (JTAG) Instructions Supported by Cyclone III Device Family (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern to be output at the device pins. Also used by the SignalTap® II
embedded logic analyzer.
SAMPLE/PRELOAD
00 0000 0101
Allows the external circuitry and board-level interconnects to be tested
by forcing a test pattern at the output pins and capturing test results at
the input pins.
(1)
EXTEST
BYPASS
00 0000 1111
Places the 1-bit bypass register between the TDIand TDOpins, which
allows the BST data to pass synchronously through selected devices to
adjacent devices during normal device operation.
11 1111 1111
00 0000 0111
00 000 0110
Selects the 32-bit USERCODEregister and places it between the TDIand
USERCODE
IDCODE
TDOpins, allowing the USERCODEto be serially shifted out of TDO
Selects the IDCODEregister and places it between TDIand TDO
allowing the IDCODEto be serially shifted out of TDO IDCODEis the
.
,
.
default instruction at power up and in TAP RESETstate.
Places the 1-bit bypass register between the TDIand TDOpins, which
allows the BST data to pass synchronously through selected devices to
adjacent devices during normal device operation, while tri-stating all of
the I/O pins.
HIGHZ
CLAMP
00 0000 1011
00 0000 1010
—
Places the 1-bit bypass register between the TDIand TDOpins, which
allows the BST data to pass synchronously through selected devices to
adjacent devices during normal device operation while holding I/O pins
to a state defined by the data in the boundary scan register.
Used when configuring Cyclone III device family using the JTAG port
with a USB-Blaster™ ByteBlaster™ II, MasterBlaster™ or ByteBlasterMV™
download cable, or when using a Jam File, or JBC File via an embedded
processor.
ICR Instructions
PULSE_NCONFIG
Emulates pulsing the nCONFIGpin low to trigger reconfiguration even
though the physical pin is unaffected.
00 0000 0001
00 0000 1101
Allows I/O reconfiguration through JTAG ports using the IOCSRfor
JTAG testing. This is executed after or during configurations. nSTATUS
pin must go high before you can issue the CONFIG_IOinstruction.
(2)
CONFIG_IO
Allows CLKUSRpin signal to replace the internal oscillator as the
configuration clock source.
(2)
EN_ACTIVE_CLK
01 1110 1110
10 1110 1110
10 1101 0000
10 1011 0000
Allows you to revert the configuration clock source from CLKUSRpin
signal set by EN_ACTIVE_CLKback to the internal oscillator.
(2)
DIS_ACTIVE_CLK
Places the active configuration mode controllers into idle state prior to
CONFIG_IOto configure the IOCSRor perform board level testing.
(2)
ACTIVE_DISENGAGE
This instruction might be used in AS and AP configuration schemes to
re-engage the active controller.
(2)
ACTIVE_ENGAGE
Places the 22-bit active boot address register between the TDIand TDO
pins, allowing a new active boot address to be serially shifted into TDI
and into the active parallel (AP) flash controller. In remote system
upgrade, the PFC_BOOT_ADDRinstruction sets the boot address for the
factory configuration.
(2), (3)
APFC_BOOT_ADDR
10 0111 0000
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
