欢迎访问ic37.com |
会员登录 免费注册
发布采购

DIFFCLK_4P 参数 Datasheet PDF下载

DIFFCLK_4P图片预览
型号: DIFFCLK_4P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号DIFFCLK_4P的Datasheet PDF文件第193页浏览型号DIFFCLK_4P的Datasheet PDF文件第194页浏览型号DIFFCLK_4P的Datasheet PDF文件第195页浏览型号DIFFCLK_4P的Datasheet PDF文件第196页浏览型号DIFFCLK_4P的Datasheet PDF文件第198页浏览型号DIFFCLK_4P的Datasheet PDF文件第199页浏览型号DIFFCLK_4P的Datasheet PDF文件第200页浏览型号DIFFCLK_4P的Datasheet PDF文件第201页  
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family  
9–39  
Configuration Features  
Figure 9–17 shows the timing waveform for a PS configuration when using an  
external host device as an external host.  
(1)  
Figure 9–17. PS Configuration Timing Waveform  
tCF2ST1  
tCFG  
tCF2CK  
nCONFIG  
nSTATUS (2)  
tSTATUS  
tCF2ST0  
tCLK  
CONF_DONE (3)  
t
CH tCL  
tCF2CD  
tST2CK  
DCLK  
(4)  
tDH  
DATA[0]  
(5)  
Bit 0 Bit 1 Bit 2 Bit 3  
tDSU  
Bit n  
User I/O Tri-stated with internal pull-up resistor  
INIT_DONE  
User Mode  
tCD2UM  
Notes to Figure 9–17:  
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG  
, nSTATUS, and CONF_DONE  
are at logic-high levels. When nCONFIGis pulled low, a reconfiguration cycle begins.  
(2) After power-up, the Cyclone III device family holds nSTATUSlow during POR delay.  
(3) After power-up, before and during configuration, CONF_DONEis low.  
(4) In user mode, drive DCLKeither high or low when using the PS configuration scheme, whichever is more convenient.  
When using the AS configuration scheme, DCLKis a Cyclone III device family output pin and must not be driven  
externally.  
(5) Do not leave the DATA[0]pin floating after configuration. Drive it high or low, whichever is more convenient.  
Table 9–13 lists the PS configuration timing parameters for Cyclone III device family.  
Table 9–13. PS Configuration Timing Parameters for Cyclone III Device Family (Part 1 of 2)  
Symbol  
tCF2CD  
tCF2ST0  
tCFG  
Parameter  
nCONFIGlow to CONF_DONElow  
nCONFIGlow to nSTATUSlow  
nCONFIGlow pulse width  
Minimum  
Maximum  
500  
Unit  
ns  
500  
ns  
500  
45  
ns  
(1)  
tSTATUS  
tCF2ST1  
tCF2CK  
tST2CK  
tDSU  
nSTATUSlow pulse width  
800  
s  
s  
s  
s  
ns  
(2)  
nCONFIGhigh to nSTATUShigh  
nCONFIGhigh to first rising edge on DCLK  
nSTATUShigh to first rising edge of DCLK  
Data setup time before rising edge on DCLK  
Data hold time after rising edge on DCLK  
DCLKhigh time  
800  
(1)  
800  
2
5
tDH  
0
ns  
tCH  
3.2  
ns  
tCL  
DCLKlow time  
3.2  
ns  
tCLK  
DCLKperiod  
7.5  
ns  
(4)  
fMAX  
DCLKfrequency  
300  
100  
MHz  
s  
(3)  
tCD2UM  
tCD2CU  
CONF_DONEhigh to user mode  
650  
CONF_DONEhigh to CLKUSRenabled  
4 × maximum DCLKperiod  
August 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1