Chapter 8: External Memory Interfaces in the Cyclone III Device Family
8–9
Cyclone III Device Family Memory Interfaces Pin Support
(1)
Figure 8–2. DQS, CQ, or CQ# Pins in Cyclone III Device Family I/O Banks
SD/CQT1#
3
DS4C5/QT
SD/CQT5#
SD2/C3QT
SD0/C1QT
I/O Bank 8
I/O Bank 7
/IOBank6
DQS2L/CQ3L
DQS0L/CQ1L
DQS2R/CQ3R
DQS0R/CQ1R
/IOBank1
Cyclone III Device Family
DQS1R/CQ1R#
DQS3R/CQ3R#
/IOBank5
DQS1L/CQ1L#
DQS3L/CQ3L#
/IOBank2
I/O Bank 3
I/O Bank 4
Q
DS2C3/QB
SD0/C1QB
SD/CQB3#
1
DS/QBC5#
Note to Figure 8–2:
(1) The DQS, CQ, or CQ# pin locations in this diagram apply to all packages in Cyclone III device family except devices in 144-pin EQFP and 164-pin
MBGA.
Figure 8–3 shows the location and numbering of the DQS, DQ, or CQ# pins in I/O
banks of the Cyclone III device in the 144-pin EQFP and 164-pin MBGA packages
only.
Figure 8–3. DQS, CQ, or CQ# Pins for Devices in the 144-Pin EQFP and 164-Pin MBGA Packages
SD/CQT1#
SD0/C1QT
I/O Bank 8
I/O Bank 7
/IOBank6
DQS0R/CQ1R
DQS0L/CQ1L
/IOBank1
Cyclone III Devices
in 144-pin EQFP and
164-pin MBGA
/IOBank5
DQS1L/CQ1L#
DQS1R/CQ1R#
/IOBank2
I/O Bank 3
I/O Bank 4
SD0/C1QB
SD/CQB1#
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
