11–6
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Error Detection Timing
Table 11–5 lists the minimum and maximum error detection frequencies.
Table 11–5. Minimum and Maximum Error Detection Frequencies
Error
Detection
Frequency
Maximum Error
Detection
Frequency
Minimum Error
Detection
Frequency
Device Type
Valid Divisors (2 )
Cyclone III
device family
80 MHz/2n
80 MHz
312.5 kHz
0, 1, 2, 3, 4, 5, 6, 7, 8
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (for more information, refer to “Software Support” on page 11–7). The
divisor is a power of two (2), where n is between 0 and 8. The divisor ranges from one
through 256. Refer to Equation 11–1.
Equation 11–1. Error Detection Frequency
80 MHz
Error detection frequency = --------------------
2n
CRC calculation time depends on the device and the error detection clock frequency.
Table 11–6 lists the estimated time for each CRC calculation with minimum and
maximum clock frequencies for Cyclone III device family.
Table 11–6. CRC Calculation Time
Maximum Time (s)
(1)
Device
Minimum Time (ms)
(2)
EP3C5
EP3C10
5
2.29
2.29
5
EP3C16
7
3.17
EP3C25
9
4.51
Cyclone III
EP3C40
15
23
31
45
42
42
79
79
7.48
EP3C55
11.77
15.81
22.67
21.24
21.24
40.27
40.27
EP3C80
EP3C120
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
Cyclone III LS
Notes to Table 11–6:
(1) The minimum time corresponds to the maximum error detection clock frequency and may vary with different
processes, voltages, and temperatures (PVT).
(2) The maximum time corresponds to the minimum error detection clock frequency and may vary with different PVT.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
