Using IEEE Std. 1149.1 BST Circuitry
Figure 14–13. JTAG Chain of Mixed Voltages
Must be
3.3 V
tolerant
TDI
3.3 V
2.5 V
V
V
CCIO
CCIO
Tester
TDO
1.5 V
1.8 V
Level
Shifter
V
V
CCIO
CCIO
Shift TDO to
level accepted by
tester if necessary
Must be
1.8 V
tolerant
Must be
2.5 V
tolerant
Cyclone II devices have dedicated JTAG pins, and the IEEE Std. 1149.1
BST circuitry is enabled upon device power-up. You can perform BST on
Cyclone II FPGAs not only before and after configuration, but also during
configuration. Cyclone II FPGAs support the BYPASS, IDCODE,and
SAMPLEinstructions during configuration without interrupting
configuration. To send all other JTAG instructions, you must interrupt
configuration using the CONFIG_IOinstruction.
Using IEEE Std.
1149.1 BST
Circuitry
The CONFIG_IOinstruction allows you to configure I/O buffers via the
JTAG port, and when issued, interrupts configuration. This instruction
allows you to perform board-level testing prior to configuring the
Cyclone II FPGA or waiting for a configuration device to complete
configuration. Once configuration has been interrupted and JTAG BST is
complete, the part must be reconfigured via JTAG (PULSE_CONFIG
instruction) or by pulsing nCONFIGlow.
When you perform JTAG boundary-scan testing before configuration, the
nCONFIGpin must be held low.
The device-wide reset (DEV_CLRn) and device-wide output enable
(DEV_OE) pins on Cyclone II devices do not affect JTAG boundary-scan or
configuration operations. Toggling these pins does not disrupt BST
operation any more than usual.
14–16
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
ALTERA [ ALTERA CORPORATION ]
