Architecture
See the Cyclone II Memory Blocks chapter in Volume 1 of the Cyclone II
Device Handbook for more information on Cyclone II M4K memory
blocks.
f
Refer to AN 306: Techniques for Implementing Multipliers in FPGA Devices
for more information on soft multipliers.
Each embedded multiplier consists of the following elements:
Architecture
■
■
■
Multiplier stage
Input and output registers
Input and output interfaces
Figure 12–2 shows the multiplier block architecture.
Figure 12–2. Multiplier Block Architecture
signa (1)
signb (1)
aclr
clock
ena
D
Q
Q
Data A
Data B
ENA
Data Out
D
Q
CLRN
ENA
CLRN
D
ENA
Output
Register
Input
Register
CLRN
Embedded Multiplier Block
Note to Figure 12–2:
(1) If necessary, you can send these signals through one register to match the data
signal path.
Input Registers
You can send each multiplier input signal into an input register or directly
into the multiplier in 9- or 18-bit sections depending on the operational
mode of the multiplier. You can send each multiplier input signal through
a register independently of each other (e.g., you can send the multiplier’s
12–4
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
ALTERA [ ALTERA CORPORATION ]
