DC & Switching Characteristics
Table 5–102 shows the JTAG timing parameters and values for Stratix II
devices.
Table 5–102. Stratix II JTAG Timing Parameters & Values
Symbol
tJCP
Parameter
TCKclock period
Min
30
13
13
3
Max Unit
ns
ns
ns
ns
ns
tJCH
TCKclock high time
tJCL
TCKclock low time
tJPSU
tJPH
JTAG port setup time
JTAG port hold time
5
tJPCO
tJPZX
tJPXZ
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
11 (1)
14 (1)
14 (1)
ns
ns
ns
Note to Table 5–102:
(1) A 1 ns adder is required for each VCC IO voltage step down from 3.3 V. For
example, tJPCO = 12 ns if VC CIO of the TDO I/O bank = 2.5 V, or 13 ns if it equals
1.8 V.
Table 5–103 shows the revision history for this chapter.
Document
Revision History
Table 5–103. Document Revision History (Part 1 of 3)
Date and
Document
Version
Changes Made
Summary of Changes
April 2011, v4.5 Updated Table 5–3.
Added operating junction temperature
for military use.
July 2009, v4.4
May 2007, v4.3
Updated Table 5–92.
Updated the spread spectrum
modulation frequency (fSS) from
(100 kHz–500 kHz) to
(30 kHz–150 kHz).
●
●
●
Updated RCONF in Table 5–4.
Updated fIN (min) in Table 5–92.
Updated fIN and fINPFD in Table 5–93.
—
Moved the Document Revision History section to the
end of the chapter.
—
Altera Corporation
April 2011
5–97
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
