I/O Structure
Figure 2–47. Row I/O Block Connection to the Interconnect Note (1)
R4 & R24
Interconnects
C4 Interconnect
I/O Block Local
Interconnect
32 Data & Control
Signals from
Logic Array (1)
32
LAB
Horizontal
I/O Block
io_dataina[3..0]
io_datainb[3..0]
Direct Link
Interconnect
to Adjacent LAB
Direct Link
Interconnect
to Adjacent LAB
Horizontal I/O
Block Contains
up to Four IOEs
io_clk[7:0]
LAB Local
Interconnect
Note to Figure 2–47:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0]and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
2–72
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
