High-Speed I/O Specifications
Table 5–91 shows the high-speed I/O timing specifications for -5 speed
grade Stratix II devices.
Table 5–91. High-Speed I/O Specifications for -5 Speed Grade
Notes (1), (2)
-5 Speed Grade
Min Typ Max
Symbol
Conditions
Unit
fHSCLK (clock frequency) W = 2 to 32 (LVDS, HyperTransport technology)
16
420
MHz
(3)
fHSCLK = fHSDR / W
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
16
150
150
(4)
500
640
840
700
500
840
200
-
MHz
MHz
Mbps
Mbps
Mbps
Mbps
ps
fHSDR (data rate)
(4)
fHSDRDPA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
150
-
TCCS
All differential I/O standards
All differential I/O standards
SW
440
ps
Output jitter
Output tRISE
Output tFALL
tDUTY
190
290
290
55
ps
All differential I/O standards
All differential I/O standards
ps
ps
45
50
%
DPA run length
DPA jitter tolerance
DPA lock time
6,400
UI
Data channel peak-to-peak jitter
0.44
UI
Standard
Training
Pattern
Transition
Density
Numberof
repetitions
SPI-4
0000000000
1111111111
10%
256
Parallel Rapid I/O
Miscellaneous
00001111
10010000
10101010
01010101
25%
50%
256
256
256
256
100%
Notes to Table 5–91:
(1) When J = 4 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
5–90
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
