DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II DDIO
row output clock on a –3 device ranges from 48.4% to 51.6%.
Table 5–83. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 & -5
Devices
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock
Port (No PLL in the Clock Path)
Row DDIO Output I/O
Standard
LVDS/
Unit
TTL/CMOS
SSTL-2
2.5 V
SSTL/HSTL HyperTransport
Technology
3.3/2.5 V
1.8/1.5 V
1.8/1.5 V
3.3 V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
440
390
375
325
430
355
350
335
330
330
180
495
450
430
385
490
410
405
390
385
390
180
170
120
105
90
160
110
95
105
75
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
90
1.8 V
100
155
75
135
100
85
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
160
85
80
70
90
65
65
105
110
105
180
60
70
60
70
LVDS/ HyperTransport
technology
180
180
Notes to Table 5–83:
(1) Table 5–83 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
1.2-V
HSTL
Unit
TTL/CMOS
SSTL-2
SSTL/HSTL
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
1.2 V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
260
210
195
380
330
315
145
100
85
145
100
85
145
100
85
ps
ps
ps
Altera Corporation
April 2011
5–83
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
