Stratix II Architecture
Figure 2–61. Fast PLL & Channel Layout in the EP2S60 to EP2S180 Devices Note (1)
Fast
Fast
PLL 7
PLL 10
2
2
4
4
LVDS
Clock
DPA
Clock
DPA
Clock
LVDS
Clock
Quadrant
Quadrant
4
4
2
2
2
Fast
PLL 1
Fast
PLL 4
Fast
PLL 2
Fast
PLL 3
2
LVDS
Clock
DPA
Clock
DPA
Clock
LVDS
Clock
Quadrant
Quadrant
4
4
2
2
Fast
PLL 8
Fast
PLL 9
Note to Figure 2–61:
(1) See Tables 2–22 through 2–26 for the number of channels each device supports.
Altera Corporation
2–103
May 2007
Stratix II Device Handbook, Volume 1