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CLK3_1N 参数 Datasheet PDF下载

CLK3_1N图片预览
型号: CLK3_1N
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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12. IEEE 1149.1 (JTAG) Boundary-Scan  
Testing for the Cyclone III Device Family  
December 2011  
CIII51014-2.3  
CIII51014-2.3  
This chapter provides guidelines on using the IEEE Std. 1149.1 boundary-scan test  
(BST) circuitry in Cyclone® III device family (Cyclone III and Cyclone III LS devices).  
BST architecture tests pin connections without using physical test probes, and  
captures functional data while a device is operating normally. Boundary-scan cells  
(BSCs) in a device can force signals onto pins or capture data from pin or logic array  
signals. Forced test data is serially shifted into the boundary-scan cells. Captured data  
is serially shifted out and externally compared to expected results.  
This chapter contains the following sections:  
“IEEE Std. 1149.1 BST Architecture” on page 12–1  
“IEEE Std. 1149.1 BST Operation Control” on page 12–2  
“I/O Voltage Support in a JTAG Chain” on page 12–5  
“Guidelines for IEEE Std. 1149.1 BST” on page 12–6  
“Boundary-Scan Description Language Support” on page 12–7  
IEEE Std. 1149.1 BST Architecture  
Cyclone III device family operating in the IEEE Std. 1149.1 BST mode use four  
required pins:  
TDI  
TDO  
TMS  
TCK  
The TCKpin has an internal weak pull-down resistor, while the TDIand TMSpins have  
weak internal pull-up resistors. The TDOoutput pin and all the JTAG input pins are  
powered by the VCCIO supply of bank 1A. All user I/O pins are tri-stated during JTAG  
configuration.  
1
For recommendations on how to connect a JTAG chain with multiple voltages across  
the devices in the chain, refer to “I/O Voltage Support in a JTAG Chain” on page 12–5.  
f
For more information about the description and functionality of all JTAG pins,  
registers used by the IEEE Std. 1149.1 BST circuitry, and the test access port (TAP)  
controller, refer to AN39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.  
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos  
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as  
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its  
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and  
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service  
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying  
on any published information and before placing orders for products or services.  
ISO  
9001:2008  
Registered  
Cyclone III Device Handbook  
Volume 1  
December 2011  
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