Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–59
Configuration Features
If you configure a master device with a SFL design, the master device enters user
mode even though the slave devices in the multiple device chain are not being
configured. The master device enters user mode with a SFL design even though the
CONF_DONEsignal is externally held low by the other slave devices in chain.
Figure 9–30 shows the JTAG configuration of a single Cyclone III device family with a
SFL design.
Figure 9–30. Programming Serial Configuration Devices In-System Using the JTAG Interface
V
CCA
(9)
V
(1)
CCIO
V
CCA
10 kΩ
V
(1)
CCIO
Cyclone III Device Family
(9)
10 kΩ
Serial Configuration
nCE (4)
TCK
TDO
V
(1)
Device
CCIO
GND
N.C. (5)
nCEO
10 kΩ
TMS
TDI
Download Cable 10-Pin Male
Header (Top View)
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
DATA[0]
Serial
Flash
Loader
(2)
25 Ω (7)
Pin 1
V
(6)
CCA
DATA
DCLK
nCS
DCLK
nCSO (8)
ASDO (8)
ASDI
GND
(3)
V
IO
1 kΩ
GND
GND
Notes to Figure 9–30:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]for
AS configuration schemes, refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the
device. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In ByteBlasterMV,
this pin is a no connect. In USB-Blaster, ByteBlaster II, and Ethernet Blaster, this pin is connected to nCEwhen it is
used for AS programming, otherwise it is a no connect.
(4) The nCEpin must be connected to GND or driven low for successful JTAG configuration.
(5) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(6) Power up the VCC of the ByteBlaster II, USB-Blaster, ByteBlasterMV, or Ethernet Blaster cable with a 2.5-V supply from
V
CCA. Third-party programmers must switch to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster
cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V
from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide.
(7) Connect the series resistor at the near end of the serial configuration device.
(8) These are dual-purpose I/O pins. The nCSOpin functions as the FLASH_NCEpin in AP mode. The ASDOpin functions
as the DATA[1]pin in other AP and FPP modes.
(9) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your
setup.
ISP of the Configuration Device
In the second stage, the SFL design in the master device allows you to write the
configuration data for the device chain into the serial configuration device with the
Cyclone III device family JTAG interface. The JTAG interface sends the programming
data for the serial configuration device to the Cyclone III device family first. The
Cyclone III device family then uses the ASMI pins to send the data to the serial
configuration device.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
