欢迎访问ic37.com |
会员登录 免费注册
发布采购

CLK15 参数 Datasheet PDF下载

CLK15图片预览
型号: CLK15
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号CLK15的Datasheet PDF文件第15页浏览型号CLK15的Datasheet PDF文件第16页浏览型号CLK15的Datasheet PDF文件第17页浏览型号CLK15的Datasheet PDF文件第18页浏览型号CLK15的Datasheet PDF文件第20页浏览型号CLK15的Datasheet PDF文件第21页浏览型号CLK15的Datasheet PDF文件第22页浏览型号CLK15的Datasheet PDF文件第23页  
2. Stratix II Architecture  
SII51002-4.3  
Stratix® II devices contain a two-dimensional row- and column-based  
architecture to implement custom logic. A series of column and row  
interconnects of varying length and speed provides signal interconnects  
between logic array blocks (LABs), memory block structures (M512 RAM,  
M4K RAM, and M-RAM blocks), and digital signal processing (DSP)  
blocks.  
Functional  
Description  
Each LAB consists of eight adaptive logic modules (ALMs). An ALM is  
the Stratix II device family’s basic building block of logic providing  
efficient implementation of user logic functions. LABs are grouped into  
rows and columns across the device.  
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus  
parity (576 bits). These blocks provide dedicated simple dual-port or  
single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks are  
grouped into columns across the device in between certain LABs.  
M4K RAM blocks are true dual-port memory blocks with 4K bits plus  
parity (4,608 bits). These blocks provide dedicated true dual-port, simple  
dual-port, or single-port memory up to 36-bits wide at up to 550 MHz.  
These blocks are grouped into columns across the device in between  
certain LABs.  
M-RAM blocks are true dual-port memory blocks with 512K bits plus  
parity (589,824 bits). These blocks provide dedicated true dual-port,  
simple dual-port, or single-port memory up to 144-bits wide at up to  
420 MHz. Several M-RAM blocks are located individually in the device's  
logic array.  
DSP blocks can implement up to either eight full-precision 9 × 9-bit  
multipliers, four full-precision 18 × 18-bit multipliers, or one  
full-precision 36 × 36-bit multiplier with add or subtract features. The  
DSP blocks support Q1.15 format rounding and saturation in the  
multiplier and accumulator stages. These blocks also contain shift  
registers for digital signal processing applications, including finite  
impulse response (FIR) and infinite impulse response (IIR) filters. DSP  
blocks are grouped into columns across the device and operate at up to  
450 MHz.  
Altera Corporation  
May 2007  
2–1