Stratix II Architecture
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs (Part 1
of 2)
Top Side Global & Regional
Clock Network Connectivity
Clock pins
CLK12p
v
v
v
v
v
v
v
v
v
v
v
v
CLK13p
CLK14p
CLK15p
CLK12n
CLK13n
CLK14n
CLK15n
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL 5 outputs
c0
v
v
v
v
v
v
v
v
v
v
c1
c2
c3
v
v
v
v
v
v
v
v
v
v
Altera Corporation
May 2007
2–65
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
