3–10
Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Write Port
Read Port
8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 256 × 32 1024 × 9 512 × 18 256 × 36
512 × 16
256 × 32
1024 × 9
512 × 18
256 × 36
v
v
—
—
—
v
v
—
—
—
v
v
—
—
—
v
v
—
—
—
v
v
—
—
—
v
v
—
—
—
—
—
v
v
v
—
—
v
v
v
—
—
v
v
v
In simple dual-port mode, M9K memory blocks support separate wrenand rden
signals. You can save power by keeping the rdensignal low (inactive) when not
reading. Read-during-write operations to the same address can either output “Don’t
Care” data at that location or output “Old Data”. To choose the desired behavior, set
the Read-During-Write option to either Don’t Care or Old Data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information about
this behavior, refer to “Read-During-Write Operations” on page 3–15.
Figure 3–10 shows the timing waveforms for read and write operations in simple
dual-port mode with unregistered outputs. Registering the outputs of the RAM
simply delays the
qoutput by one clock cycle.
Figure 3–10. Cyclone III Device Family Simple Dual-Port Timing Waveforms
wrclock
wren
a0
a1
a2
a3
a4
a5
an
din
an-1
a6
wraddress
data
din-1
din4
din5
din6
rdclock
rden
rdaddress
bn
doutn-1
b1
b2
b3
b0
q (asynch)
dout0
doutn
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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