Adaptive Logic Modules
Figure 2–12. Conditional Operation Example
Adder output
is not used.
ALM 1
X[0]
Y[0]
Comb &
Adder
Logic
X[0]
X[1]
R[0]
R[1]
To general or
local routing
D
D
Q
reg0
syncdata
syncload
syncload
X[1]
Y[1]
Comb &
Adder
Logic
To general or
local routing
Q
reg1
Carry Chain
ALM 2
X[2]
Y[2]
Comb &
Adder
Logic
X[2]
R[2]
To general or
local routing
D
Q
reg0
syncload
Comb &
Adder
Logic
To local routing &
then to LAB-wide
syncload
carry_out
The arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, add/subtract control, synchronous clear,
synchronous load. The LAB local interconnect data inputs generate the
clock enable, counter enable, synchronous up/down and add/subtract
control signals. These control signals are good candidates for the inputs
that are shared between the four LUTs in the ALM. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. The Quartus II software automatically places any
registers that are not used by the counter into other LABs.
Carry Chain
The carry chain provides a fast carry function between the dedicated
adders in arithmetic or shared arithmetic mode. Carry chains can begin in
either the first ALM or the fifth ALM in an LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
2–16
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
