DC & Switching Characteristics
Table 5–88 provides high-speed timing specifications definitions.
High-Speed I/O
Specifications
Table 5–88. High-Speed Timing Specifications & Definitions
High-Speed Timing Specifications
Definitions
tC
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
fHSCLK
J
W
tRISE
Low-to-high transmission time.
tFALL
High-to-low transmission time.
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).
fHSDR
Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA.
Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA.
fHSDRDPA
Channel-to-channel skew (TCCS)
The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS
measurement.
Sampling window (SW)
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Input jitter
Output jitter
tDUTY
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
tLOCK
Table 5–89 shows the high-speed I/O timing specifications for -3 speed
grade Stratix II devices.
Table 5–89. High-Speed I/O Specifications for -3 Speed Grade (Part 1 of 2)
Symbol Conditions
Notes (1), (2)
-3 Speed Grade
Unit
Min Typ Max
fHSCLK (clock frequency) W = 2 to 32 (LVDS, HyperTransport technology)
16
520
MHz
(3)
fHSCLK = fHSDR / W
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
16
500
717
MHz
MHz
150
Altera Corporation
April 2011
5–87
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
