DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II
non-DDIO row output clock on a –3 device ranges from 47.5% to 52.5%.
Table 5–81. Maximum DCD for Non-DDIO Output on Column I/O
Pins
Note (1)
Column I/O Output
Standard I/O
Standard
Maximum DCD for Non-DDIO Output
Unit
-3 Devices
-4 & -5 Devices
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
190
140
125
80
220
175
155
110
215
135
130
115
100
110
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
185
105
100
90
70
1.8-V HSTL
Class I
80
1.8-V HSTL
Class II
80
85
50
110
115
80
ps
ps
ps
1.5-V HSTL
Class I
1.5-V HSTL
Class II
1.2-V HSTL (2)
170
55
-
ps
ps
LVPECL
80
Notes to Table 5–81:
(1) The DCD specification is based on a no logic array noise condition.
(2) 1.2-V HSTL is only supported in -3 devices.
Altera Corporation
April 2011
5–81
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
