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CLK12_7N 参数 Datasheet PDF下载

CLK12_7N图片预览
型号: CLK12_7N
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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9–34  
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family  
Configuration Features  
The default configuration boot addressing allows the system to use special parameter  
blocks in the flash memory map. Parameter blocks are at the top or bottom of the  
memory map. The configuration boot address in the AP configuration scheme is  
shown in Figure 9–13. You can change the default configuration default boot address  
0x010000 to any desired address using the APFC_BOOT_ADDR JTAG instruction. For  
more information about the APFC_BOOT_ADDR JTAG instruction, refer to “JTAG  
Instructions” on page 9–60.  
Figure 9–13. Configuration Boot Address in AP Flash Memory Map  
Bottom Parameter Flash Memory  
Top Parameter Flash Memory  
128-Kb  
parameter area  
Other data/code  
Other data/code  
Cyclone III  
Default  
Boot  
Cyclone III  
Default  
Boot  
Address  
Address  
Configuration  
Data  
Configuration  
Data  
x010000 (1)  
x00FFF  
x010000 (1)  
x00FFF  
Other data/code  
16-bit word  
128-Kb  
parameter area  
16-bit word  
x000000  
x000000  
bit[15]  
bit[0]  
bit[15]  
bit[0]  
Note to Figure 9–13:  
(1) The default configuration boot address is x010000 when represented in 16-bit word addressing.  
PS Configuration  
You can perform PS configuration on Cyclone III device family with an external  
intelligent host, such as a MAX II device, microprocessor with flash memory, or a  
download cable. In the PS scheme, an external host controls the configuration.  
Configuration data is clocked into the target Cyclone III device family using the  
DATA[0]pin at each rising edge of DCLK  
.
If your system already contains a common flash interface (CFI) flash memory, you can  
use it for the Cyclone III device family configuration storage as well. The MAX II PFL  
feature provides an efficient method to program CFI flash memory devices through  
the JTAG interface and provides the logic to control the configuration from the flash  
memory device to the Cyclone III device family. Both PS and FPP configuration  
schemes are supported using the PFL feature.  
f
1
For more information about the PFL, refer to Parallel Flash Loader Megafunction User  
Guide.  
Cyclone III device family does not support enhanced configuration devices for PS or  
FPP configurations.  
Cyclone III Device Handbook  
Volume 1  
August 2012 Altera Corporation