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CDPCLK5 参数 Datasheet PDF下载

CDPCLK5图片预览
型号: CDPCLK5
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family  
10–3  
Hot-Socketing Feature Implementation  
Hot-Socketing Feature Implementation  
Each I/O pin has the circuitry shown in Figure 10–1. The hot-socketing circuit does  
not include CONF_DONE nCEO, and nSTATUSpins to ensure that they are able to operate  
,
during configuration. Thus, it is expected behavior for these pins to drive out during  
power up and power down sequences.  
Figure 10–1 shows the hot-socketing circuit block diagram for Cyclone III device  
family.  
Figure 10–1. Hot-socketing Circuit Block Diagram for Cyclone III Device Family  
Power On  
Reset  
Monitor  
VCCIO  
Weak  
Pull-Up  
Resistor  
R
Output Enable  
Voltage  
Tolerance  
Control  
Hot Socket  
PAD  
Output  
Pre-Driver  
Input Buffer  
to Logic Array  
The POR circuit monitors the voltage level of power supplies and keeps the I/O pins  
tristated until the device is in user mode. The weak pull-up resistor (R) in Cyclone III  
device family I/O element (IOE) keeps the I/O pins from floating. The 3.3-V tolerance  
control circuit permits the I/O pins to be driven by 3.3 V before VCCIO, VCC, and VCCA  
supplies are powered up, and it prevents the I/O pins from driving out when the  
device is not in user mode.  
1
Altera uses GND as reference for hot-socketing operation and I/O buffer designs. To  
ensure proper operation, Altera recommends connecting the GND between boards  
before connecting the power supplies. This prevents the GND on your board from  
being pulled up inadvertently by a path to power through other components on your  
board. A pulled up GND can otherwise cause an out-of-specification I/O voltage or  
current condition with the Altera® device.  
POR Circuitry  
Cyclone III device family contains POR circuitry to keep the device in a reset state  
until the power supply voltage levels have stabilized during power up. During POR,  
all user I/O pins are tristated until the VCC reaches the recommended operating  
levels. In addition, the POR circuitry also ensures the VCCIO level of I/O banks 1, 6, 7,  
and 8 that contains configuration pins reach an acceptable level before configuration  
is triggered.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1