Chapter 3: DC and Switching Characteristics for MAX V Devices
3–17
Timing Model and Specifications
Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 2 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Symbol
Parameter
Unit
C4
C5, I5
C4 C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Minimum erasesignal
to address clock hold
time
tAE
0
—
0
—
0
—
0
—
ns
ns
Maximum delay between
the eraserising edge to
the UFM busysignal
rising edge
tEB
—
20
960
—
—
20
960
—
—
20
960
—
—
20
960
—
Minimum delay allowed
from the UFM busy
signal going low to
tBE
ns
erasesignal going low
Maximum length of busy
pulse during an erase
tEPMX
—
—
500
5
—
—
500
5
—
—
500
5
—
—
500
5
ms
ns
Delay from data register
clock to data register
output
tDCO
Delay from OSC_ENA
signal reaching UFM to
rising clock of OSC
leaving the UFM
tOE
180
—
—
65
—
180
—
—
65
—
180
—
—
65
—
180
—
—
65
—
ns
ns
ns
Maximum read access
time
tRA
Maximum delay between
the OSC_ENArising edge
to the erase/program
signal rising edge
tOSCS
250
250
250
250
Minimum delay allowed
from the
erase/programsignal
going low to OSC_ENA
signal going low
tOSCH
250
—
250
—
250
—
250
—
ns
May 2011 Altera Corporation
MAX V Device Handbook
ALTERA [ ALTERA CORPORATION ]
