6. JTAG and In-System Programmability
in MAX V Devices
May 2011
MV51006-1.1
MV51006-1.1
This chapter describes the IEEE Standard 1149.1 JTAG BST circuitry that is supported
in MAX® V devices and how you can enable concurrent in-system programming of
multiple devices in a minimum time with the IEEE Standard 1532 in-system
programmability (ISP). This chapter also describes the programming sequence, types
of programming with the Quartus® II software or external hardware, and design
security.
This chapter includes the following sections:
■
■
“IEEE Std. 1149.1 Boundary-Scan Support” on page 6–1
“In-System Programmability” on page 6–5
IEEE Std. 1149.1 Boundary-Scan Support
All MAX V devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-2001 specification. You can only perform JTAG boundary-scan
testing after you have fully powered the VCCINT and all VCCIO banks and a certain
amount of configuration time (tCONFIG) have passed. For in-system programming,
MAX V devices can use the JTAG port with either the Quartus II software or
hardware with Programmer Object File (.pof), Jam™ Standard Test and Programming
Language (STAPL) Format File (.jam), or Jam Byte Code Files (.jbc).
JTAG pins support 1.5-V, 1.8-V, 2.5-V, and 3.3-V I/O standards. The VCCIO of the bank
where it is located determines the supported voltage level and standard. The
dedicated JTAG pins reside in Bank 1 of all MAX V devices.
Table 6–1 lists the JTAG instructions supported in MAX V devices.
Table 6–1. JTAG Instructions for MAX V Devices (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
Allows you to capture and examine a snapshot of signals at the
device pins if the device is operating in normal mode. Permits an
initial data pattern to be an output at the device pins.
SAMPLE/PRELOAD
00 0000 0101
Allows you to test the external circuitry and board-level
interconnects by forcing a test pattern at the output pins and
capturing test results at the input pins.
EXTEST (1)
00 0000 1111
11 1111 1111
Places the 1-bit bypass register between the TDIand TDOpins,
which allows the boundary-scan test (BST) data to pass
synchronously through target devices to adjacent devices during
normal device operation.
BYPASS
Selects the 32-bit USERCODEregister and places it between the TDI
and TDOpins, allowing you to shift the USERCODEregister out of the
TDOpin serially. If you do not specify the USERCODEin the Quartus II
software, the 32-bit USERCODEregister defaults to all 1’s.
USERCODE
00 0000 0111
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MAX V Device Handbook
May 2011
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