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5M80ZT100C5 参数 Datasheet PDF下载

5M80ZT100C5图片预览
型号: 5M80ZT100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: MAX V Architecture  
2–31  
I/O Structure  
The 5M1270Z and 5M2210Z devices support four I/O banks, as shown in Figure 2–23.  
Each of these banks support all of the LVTTL, LVCMOS, LVDS, and RSDS standards  
shown in Table 2–4. PCI compliant I/O is supported in Bank 3. Bank 3 supports the  
PCI clamping diode on inputs and PCI drive compliance on outputs. You must use  
Bank 3 for designs requiring PCI compliant I/O pins. The Quartus II software  
automatically places I/O pins in this bank if assigned with the PCI I/O standard.  
Figure 2–23. I/O Banks for 5M1270Z and 5M2210Z Devices (Note 1), (2)  
I/O Bank 2  
Also Supports  
the 3.3-V PCI  
I/O Standard  
All I/O Banks Support  
3.3-V LVTTL/LVCMOS,  
2.5-V LVTTL/LVCMOS,  
1.8-V LVTTL/LVCMOS,  
1.5-V LVCMOS,  
I/O Bank 1  
I/O Bank 3  
1.2-V LVCMOS (3),  
LVDS (4),  
RSDS(5)  
I/O Bank 4  
Notes to Figure 2–23:  
(1) Figure 2–23 is a top view of the silicon die.  
(2) Figure 2–23 is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations.  
(3) This I/O standard is not supported in Bank 1.  
(4) Emulated LVDS output using a three resistor network (LVDS_E_3R).  
(5) Emulated RSDS output using a three resistor network (RSDS_E_3R).  
Each I/O bank has dedicated VCCIO pins that determine the voltage standard support  
in that bank. A single device can support 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces;  
each individual bank can support a different standard. Each I/O bank can support  
multiple standards with the same VCCIO for input and output pins. For example, when  
VCCIO is 3.3 V, Bank 3 can support LVTTL, LVCMOS, and 3.3-V PCI. VCCIO powers  
both the input and output buffers in MAX V devices.  
The JTAG pins for MAX V devices are dedicated pins that cannot be used as regular  
I/O pins. The pins TMS, TDI, TDO, and TCKsupport all the I/O standards shown in  
Table 2–4 on page 2–29 except for PCI and 1.2-V LVCMOS. These pins reside in Bank 1  
for all MAX V devices and their I/O standard support is controlled by the VCCIO  
setting for Bank 1.  
December 2010 Altera Corporation  
MAX V Device Handbook  
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