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5M80ZT100C5 参数 Datasheet PDF下载

5M80ZT100C5图片预览
型号: 5M80ZT100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–3  
UFM Functional Description  
UFM Functional Description  
Figure 7–1 is the block diagram of the MAX V UFM block and the interface signals.  
Figure 7–1. UFM Block and Interface Signals  
UFM Block  
PROGRAM  
ERASE  
RTP_BUSY  
BUSY  
Program  
Erase  
Control  
_
:
OSC_ENA  
OSC  
4
OSC  
UFM Sector 1  
UFM Sector 0  
9
ARCLK  
Address  
Register  
16  
16  
ARSHFT  
ARDin  
DRDin  
Data Register  
DRDout  
DRCLK  
DRSHFT  
Table 7–4 lists the MAX V UFM block input and output interface signals.  
Table 7–4. UFM Interface Signals (Part 1 of 2)  
Port Name  
Port Type  
Description  
Serial input to the data register. It is used to enter a data word when writing to the UFM. The  
data register is 16 bits wide and data is shifted serially from the LSB to the MSB with each  
DRCLK. This port is required for writing, but unused if the UFM is in read-only mode.  
DRDin  
Input  
Clock input that controls the data register. It is required and takes control when data is  
shifted from DRDinto DRDoutor loaded in parallel from the flash memory. The maximum  
frequency for DRCLKis 10 MHz.  
DRCLK  
Input  
Input  
Signal that determines whether to shift the data register or load it on a DRCLKedge. A high  
value shifts the data from DRDininto the LSB of the data register and from the MSB of the  
data register out to DRDout. A low value loads the value of the current address in the flash  
memory to the data register.  
DRSHFT  
Serial input to the address register. It is used to enter the address of a memory location to  
read, program, or erase. The address register is 9 bits wide for the UFM size of 8,192 bits.  
ARDin  
ARCLK  
Input  
Input  
Clock input that controls the address register. It is required when shifting the address data  
from ARDininto the address register or during the increment stage. The maximum  
frequency for ARCLKis 10 MHz.  
Signal that determines whether to shift the address register or increment it on an ARCLK  
edge. A high value shifts the data from ARDinserially into the address register. A low value  
increments the current address by 1. The address register rolls over to 0 when the address  
space is at the maximum.  
ARSHFT  
Input  
January 2011 Altera Corporation  
MAX V Device Handbook  
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