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5M40ZF64I5N 参数 Datasheet PDF下载

5M40ZF64I5N图片预览
型号: 5M40ZF64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: MAX V器件手册 [MAX V Device Handbook]
分类和应用:
文件页数/大小: 166 页 / 4016 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–8  
Chapter 5: Using MAX V Devices in Multi-Voltage Systems  
Power-Up Sequencing  
1
For signals with a duty cycle greater than 30% on MAX V input pins, Altera  
recommends using a VCCIO voltage of 3.0 V to guarantee long-term I/O reliability. For  
signals with a duty cycle less than 30%, the VCCIO voltage can be 3.3 V.  
Power-Up Sequencing  
MAX V devices are designed to operate in multi-voltage environments where it may  
be difficult to control power sequencing. Therefore, MAX V devices are designed to  
tolerate any possible power-up sequence. Either VCCINT or VCCIO can initially supply  
power to the device and 3.3-, 2.5-, 1.8-, 1.5-, or 1.2-V input signals can drive the  
devices without special precautions before VCCINT or VCCIO is applied. MAX V devices  
can operate with a VCCIO voltage level that is higher than the VCCINT level.  
When VCCIO and VCCINT are supplied from different power sources to a MAX V  
device, a delay between VCCIO and VCCINT may occur. Normal operation does not  
occur until both power supplies are in their recommended operating range. When  
VCCINT is powered-up, the IEEE Std. 1149.1 JTAG circuitry is active. If TMSand TCKare  
connected to VCCIO and VCCIO is not powered-up, the JTAG signals are left floating.  
Thus, any transition on TCKcan cause the state machine to transition to an unknown  
JTAG state, leading to incorrect operation when VCCIO is finally powered-up. To  
disable the JTAG state during the power-up sequence, pull TCKlow to ensure that an  
inadvertent rising edge does not occur on TCK  
.
Document Revision History  
Table 5–4 lists the revision history for this chapter.  
Table 5–4. Document Revision History  
Date  
Version  
Changes  
December 2010  
1.0  
Initial release.  
MAX V Device Handbook  
December 2010 Altera Corporation