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5M2210ZF256C5N 参数 Datasheet PDF下载

5M2210ZF256C5N图片预览
型号: 5M2210ZF256C5N
PDF下载: 下载PDF文件 查看货源
内容描述: 3.直流和开关特性的MAX V器件 [3. DC and Switching Characteristics for MAX V Devices]
分类和应用: 可编程逻辑器件开关LTEPC时钟
文件页数/大小: 30 页 / 489 K
品牌: ALTERA [ ALTERA CORPORATION ]
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3–30  
Chapter 3: DC and Switching Characteristics for MAX V Devices  
Document Revision History  
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)  
Symbol  
Parameter  
Min  
Max  
Unit  
tJSXZ  
Notes to Table 3–41:  
(1) Minimum clock period specified for 10 pF load on the TDOpin. Larger loads on TDOdegrades the maximum TCKfrequency.  
Update register valid output to high impedance  
25  
ns  
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and  
1.5-V LVCMOS operation, the tJPSU minimum is 6 ns and tJPCO, tJPZX, and tJPXZ are maximum values at 35 ns.  
Document Revision History  
Table 3–42 lists the revision history for this chapter.  
Table 3–42. Document Revision History  
Date  
May 2011  
Version  
1.2  
Changes  
Updated Table 3–2, Table 3–15, Table 3–16, and Table 3–33.  
Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.  
Initial release.  
January 2011  
1.1  
December 2010  
1.0  
MAX V Device Handbook  
May 2011 Altera Corporation  
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