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5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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3–12  
Chapter 3: DC and Switching Characteristics for MAX V Devices  
Timing Model and Specifications  
Table 3–17. Device Performance for MAX V Devices (Part 2 of 2)  
Resources Used  
Performance  
5M40Z/ 5M80Z/ 5M160Z/  
5M1270Z/ 5M2210Z  
Resource  
Used  
Design Size and  
Function  
5M240Z/ 5M570Z  
Unit  
UFM  
Blocks  
Mode  
LEs  
C4  
C5, I5  
C4  
C5, I5  
512 × 16  
512 × 16  
None  
3
1
1
10.0  
9.7  
10.0  
9.7  
10.0  
8.0  
10.0  
8.0  
MHz  
MHz  
SPI (2)  
37  
UFM  
Parallel  
(3)  
I2C (3)  
512 × 8  
73  
1
1
(4)  
(4)  
(4)  
(4)  
MHz  
kHz  
512 × 16  
142  
100 (5)  
100 (5)  
100 (5)  
100 (5)  
Notes to Table 3–17:  
(1) This design is a binary loadable up counter.  
(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of logic elements (LEs) used.  
(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.  
(4) This design is asynchronous.  
(5) The I2C megafunction is verified in hardware up to 100-kHz serial clock line rate.  
Internal Timing Parameters  
Internal timing parameters are specified on a speed grade basis independent of device  
density. Table 3–18 through Table 3–25 on page 3–19 list the MAX V device internal  
timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and  
MultiTrack interconnects.  
f For more information about each internal timing microparameters symbol, refer to  
AN629: Understanding Timing in Altera CPLDs.  
Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 1 of 2)  
5M40Z/ 5M80Z/ 5M160Z/  
5M1270Z/ 5M2210Z  
5M240Z/ 5M570Z  
Symbol  
Parameter  
Unit  
C4  
C5, I5  
Max  
C4  
C5, I5  
Min  
Max  
Min  
Min  
Max  
Min  
Max  
LE combinational look-up  
table (LUT) delay  
tLUT  
1,215  
2,247  
742  
914  
ps  
tCOMB  
tCLR  
Combinational path delay  
LE register clear delay  
LE register preset delay  
401  
401  
243  
545  
545  
309  
309  
309  
192  
381  
381  
236  
ps  
ps  
ps  
tPRE  
LE register setup time  
before clock  
tSU  
tH  
260  
0
321  
0
271  
0
333  
0
ps  
ps  
ps  
LE register hold time  
after clock  
LE register  
clock-to-output delay  
tCO  
380  
494  
305  
376  
MAX V Device Handbook  
May 2011 Altera Corporation  
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