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5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–12  
Chapter 2: MAX V Architecture  
Logic Elements  
The speed advantage of the carry-select chain is in the parallel pre-computation of  
carry chains. Because the LAB carry-in selects the precomputed carry chain, not every  
LE is in the critical path. Only the propagation delays between LAB carry-in  
generation (LE5and LE10) are now part of the critical path. This feature allows the  
MAX V architecture to implement high-speed counters, adders, multipliers, parity  
functions, and comparators of arbitrary width.  
Figure 2–9 shows the carry-select circuitry in an LAB for a 10-bit full adder. One  
portion of the LUT generates the sum of two bits using the input signals and the  
appropriate carry-in bit; the sum is routed to the output of the LE. The register can be  
bypassed for simple adders or used for accumulator functions. Another portion of the  
LUT generates carry-out bits. An LAB-wide carry-in bit selects which chain is used for  
the addition of given inputs. The carry-in signal for each chain, carry-in0or  
carry-in1, selects the carry-out to carry forward to the carry-in signal of the  
next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to  
local, row, or column interconnects.  
Figure 2–9. Carry-Select Chain  
LAB Carry-In  
0
1
LAB Carry-In  
Carry-In0  
Sum1  
Sum2  
Sum3  
Sum4  
Sum5  
A1  
B1  
LE0  
LE1  
LE2  
LE3  
LE4  
Carry-In1  
A2  
B2  
LUT  
LUT  
data1  
data2  
Sum  
A3  
B3  
A4  
B4  
LUT  
LUT  
A5  
B5  
0
1
Carry-Out0  
Carry-Out1  
Sum6  
Sum7  
Sum8  
Sum9  
Sum10  
A6  
B6  
LE5  
LE6  
LE7  
LE8  
LE9  
A7  
B7  
A8  
B8  
A9  
B9  
A10  
B10  
To top of adjacent LAB  
LAB Carry-Out  
MAX V Device Handbook  
December 2010 Altera Corporation  
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