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5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: MAX V Architecture  
2–5  
Logic Array Blocks  
adjacent LE for fast sequential LUT connections within the same LAB. Register chain  
connections transfer the output of one LE’s register to the adjacent LE’s register  
within an LAB. The Quartus® II software places associated logic within an LAB or  
adjacent LABs, allowing the use of local, LUT chain, and register chain connections  
for performance and area efficiency. Figure 2–3 shows the MAX V LAB.  
Figure 2–3. LAB Structure for MAX V Devices  
Row Interconnect  
Column Interconnect  
LE0  
LE1  
LE2  
LE3  
Fast I/O connection  
to IOE (1)  
Fast I/O connection  
to IOE (1)  
DirectLink  
DirectLink  
interconnect from  
adjacent LAB  
or IOE  
interconnect from  
adjacent LAB  
or IOE  
LE4  
LE5  
LE6  
LE7  
DirectLink  
DirectLink  
interconnect to  
adjacent LAB  
or IOE  
interconnect to  
adjacent LAB  
or IOE  
LE8  
LE9  
Logic Element  
LAB  
Local Interconnect  
Note to Figure 2–3:  
(1) Only from LABs adjacent to IOEs.  
December 2010 Altera Corporation  
MAX V Device Handbook  
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