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5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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7–18  
Chapter 7: User Flash Memory in MAX V Devices  
Software Support for UFM Block  
The ALTUFM_I2C megafunction supports four different erase operation methods  
shown on page 4 of the ALTUFM MegaWizard Plug-In Manager:  
Full Erase (Device Slave Address Triggered)  
Sector Erase (Byte Address Triggered)  
Sector Erase (A2 Triggered)  
No Erase  
These erase options only work as described if that particular option is selected in the  
MegaWizard Plug-In Manager before compiling the design files and programming  
the device. Only one option can be selected for the ALTUFM_I2C megafunction.  
Each erase option is discussed in more detail in the following sections.  
Full Erase (Device Slave Address Triggered)  
The full erase option uses the A2, A1, A0 bits of the slave address to distinguish  
between an erase or read/write operation. This slave operation decoding occurs when  
the master transfers the slave address to the slave after generating the start condition.  
If the A2, A1, and A0 slave address bits transmitted to the UFM slave equals 111 and  
the four remaining MSBs match the rest of the slave addresses, then the Full Erase  
operation is selected. If the A6, A5, A4, A3 A2, A1, and A0 slave address bits transmitted  
to the UFM match its unique slave address setting, the read/write operation is  
selected and functions as expected. As a result, this erase option utilizes two slave  
addresses on the bus reserving A6, A5, A4, A3, 1, 1, 1 as the erase trigger. Both sectors  
of the UFM block will be erased when the Full Erase operation is executed. This  
operation requires acknowledge polling. The internal UFM erase function only begins  
after the master generates a stop condition. Figure 7–13 shows the full erase sequence  
triggered by using the slave address.  
If the memory is write-protected (WP = 1), the slave does not acknowledge the erase  
trigger slave address (A6, A5, A4, A3, 1, 1, 1) sent by the master. The master should  
then send a stop condition to terminate the transfer. The full erase operation will not  
be executed.  
Figure 7–13. Full Erase Sequence Triggered Using the Slave Address  
Slave Address  
S
A
P
R/W  
A A A A 111  
6
5 4 3  
'0' (write)  
From Master to Slave  
From Slave to Master  
S – Start Condition  
P – Stop Condition  
A – Acknowledge  
MAX V Device Handbook  
January 2011 Altera Corporation  
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