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5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–5  
UFM Functional Description  
UFM Address Register  
The MAX V UFM block is organized as a 512 × 16 memory. Because the UFM block is  
organized into two sectors, the MSB of the address indicates the sector that is used; 0  
is for sector 0 (UFM0) while 1 is for sector 1 (UFM1). An ERASEinstruction erases the  
content of the specific sector that is indicated by the MSB of the address register.  
Figure 7–2 shows the selection of the UFM sector using the MSB of the address  
register.  
For more information about the erase mode, refer to “Erase” on page 7–11.  
Figure 7–2. Selection of the UFM Sector Using the MSB of the Address Register  
Sector 0  
Address Register  
UFM Block  
0
1
ARDin  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
LSB  
MSB  
UFM Block  
Sector 1  
ARClk  
Three control signals exist for the address register: ARSHFT, ARCLK, and ARDin. ARSHFTis  
used as both a shift-enable control signal and an auto-increment signal. If the ARSHFT  
signal is high, a rising edge on ARCLKloads address data serially from the ARDinport  
and moves data serially through the register. A clock edge with the ARSHFTsignal low  
increments the address register by 1. This implements an auto-increment of the  
address to allow data streaming. When a program, read, or erase sequence is  
executing, the address that is in the address register becomes the active UFM location.  
January 2011 Altera Corporation  
MAX V Device Handbook  
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