Chapter 7: User Flash Memory in MAX V Devices
7–31
Software Support for UFM Block
WREN (Write Enable)
The interface is powered-up in the write disable state. Therefore, WENin the status
register (refer to Table 7–11) is at power-up. Before any write is allowed to take
place, WRENmust be issued to set WENin the status register to . If the interface is in
0
1
read-only mode, WRENdoes not have any effect on WEN, because the status register does
not exist. After WENis set to 1, it can be reset by the WRDIinstruction; the WRITEand
SECTOR-ERASEinstructions will not reset the WENbit. WRENis issued through the
following sequence, as shown in Figure 7–28:
1. nCSis pulled low.
2. Opcode 00000110is transmitted into the interface to set WENto
1in the status
register.
3. After the transmission of the eighth bit of WREN, the interface is in wait state
(waiting for nCSto be pulled back to high). Any transmission after this is ignored.
4. nCSis pulled back to high.
Figure 7–28. WREN Operation Sequence
nCS
0
1
2
3
4
5 6 7
SCK
SI
8-bit
Instruction
06H
MSB
High Impedance
SO
January 2011 Altera Corporation
MAX V Device Handbook
ALTERA [ ALTERA CORPORATION ]
