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5M160ZT64I4N 参数 Datasheet PDF下载

5M160ZT64I4N图片预览
型号: 5M160ZT64I4N
PDF下载: 下载PDF文件 查看货源
内容描述: MAX V器件手册 [MAX V Device Handbook]
分类和应用:
文件页数/大小: 166 页 / 4016 K
品牌: ALTERA [ ALTERA CORPORATION ]
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7–26  
Chapter 7: User Flash Memory in MAX V Devices  
Software Support for UFM Block  
READ  
READis the instruction for data transmission, where the data is read from the UFM  
block. When data transfer is taking place, the MSB is always the first bit to be  
transmitted or received. The data output stream is continuous through all addresses  
until it is terminated by a low-to-high transition at the nCSport. The READoperation is  
always performed through the following sequence in SPI, as shown in Figure 7–21:  
1. nCSis pulled low to indicate the start of transmission.  
2. An 8-bit READopcode (00000011) is received from the master device. (If internal  
programming is in progress, READis ignored and not accepted).  
3. A 16-bit address is received from the master device. The LSB of the address is  
received last. Because the UFM block can take only nine bits of address maximum,  
the first seven address bits received are discarded.  
4. Data is transmitted for as many words as needed by the slave device through SO  
for READoperation. When the end of the UFM storage array is reached, the address  
counter rolls over to the start of the UFM to continue the READoperation.  
5. nCSis pulled back to high to indicate the end of transmission.  
For SPI Base mode, the READoperation is always performed through the following  
sequence in SPI:  
1. nCSis pulled low to indicate the start of transmission.  
2. An 8-bit READopcode (00000011) is received from the master device, followed by  
an 8-bit address. If internal programming is in progress, the READoperation is  
ignored and not accepted.  
3. Data is transmitted for as many words as needed by the slave device through SO  
for READoperation. The internal address pointer automatically increments until the  
highest memory address is reached (address 255 only because the UFM sector 0 is  
used). The address counter will not roll over when address 255 is reached. The SO  
output is set to high-impedance (Z) when all eight data bits from address 255 have  
been shifted out through the SOport.  
4. nCSis pulled back to high to indicate the end of transmission.  
Figure 7–21. READ Operation Sequence for Extended Mode  
nCS  
0
1
2
3
4
5
6
7
8
9
10 11  
20 21 22 23 24 25 26 27  
36 37 38 39  
SCK  
SI  
8-bit  
Instruction  
16-bit  
Address  
03H  
MSB  
MSB  
High Impedance  
SO  
16-bit Data Out 1  
16-bit Data Out 2  
MSB  
MSB  
MAX V Device Handbook  
January 2011 Altera Corporation  
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