Chapter 2: MAX V Architecture
2–9
Logic Elements
improves device utilization because the device can use the register and the LUT for
unrelated functions. Another special packing mode allows the register output to feed
back into the LUT of the same LE so that the register is packed with its own fan-out
LUT. This mode provides another mechanism for improved fitting. The LE can also
drive out registered and unregistered versions of the LUT output.
LUT Chain and Register Chain
In addition to the three general routing outputs, the LEs within a LAB have LUT chain
and register chain outputs. LUT chain connections allow LUTs within the same LAB
to cascade together for wide input functions. Register chain outputs allow registers
within the same LAB to cascade together. The register chain output allows a LAB to
use LUTs for a single combinational function and the registers for an unrelated shift
register implementation. These resources speed up connections between LABs while
saving local interconnect resources. For more information about LUT chain and
register chain connections, refer to “MultiTrack Interconnect” on page 2–14.
addnsub Signal
The LE’s dynamic adder/subtractor feature saves logic resources by using one set of
LEs to implement both an adder and a subtractor. This feature is controlled by the
LAB-wide control signal addnsub. The addnsubsignal sets the LAB to perform either
A + B or A – B. The LUT computes addition; subtraction is computed by adding the
two’s complement of the intended subtractor. The LAB-wide signal converts to two’s
complement by inverting the B bits within the LAB and setting carry-in to 1, which
adds one to the LSB. The LSB of an adder/subtractor must be placed in the first LE of
the LAB, where the LAB-wide addnsubsignal automatically sets the carry-in to 1. The
Quartus II Compiler automatically places and uses the adder/subtractor feature
when using adder/subtractor parameterized functions.
LE Operating Modes
The MAX V LE can operate in one of the following modes:
■
“Normal Mode”
■
“Dynamic Arithmetic Mode”
Each mode uses LE resources differently. In each mode, eight available inputs to the
LE, the four data inputs from the LAB local interconnect, carry-in0 and carry-in1
from the previous LE, the LAB carry-in from the previous carry-chain LAB, and the
register chain connection are directed to different destinations to implement the
desired logic function. LAB-wide signals provide clock, asynchronous clear,
asynchronous preset/load, synchronous clear, synchronous load, and clock enable
control for the register. These LAB-wide signals are available in all LE modes. The
addnsubcontrol signal is allowed in arithmetic mode.
The Quartus II software, along with parameterized functions such as the library of
parameterized modules (LPM) functions, automatically chooses the appropriate
mode for common functions such as counters, adders, subtractors, and arithmetic
functions.
December 2010 Altera Corporation
MAX V Device Handbook
ALTERA [ ALTERA CORPORATION ]
