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5CSXC6 参数 Datasheet PDF下载

5CSXC6图片预览
型号: 5CSXC6
PDF下载: 下载PDF文件 查看货源
内容描述: 旋风V器件手册 [Cyclone V Device Handbook]
分类和应用:
文件页数/大小: 74 页 / 1776 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Device Datasheet for Cyclone V Devices  
2–13  
Electrical Characteristics  
Table 2–18. Differential HSTL I/O Standards for Cyclone V Devices—Preliminary  
VCCIO (V)  
Typ  
VDIF(DC) (V)  
VX(AC) (V)  
Typ  
VCM(DC) (V)  
Typ  
VDIF(AC) (V)  
Min Max  
I/O  
Standard  
Min  
Max Min Max  
Min  
Max  
Min  
Max  
HSTL-18  
Class I, II  
1.71  
1.8  
1.89 0.2  
0.78  
1.12  
0.78  
1.12  
0.4  
0.4  
0.3  
HSTL-15  
Class I, II  
1.425 1.5 1.575 0.2  
0.68  
0.9  
0.68  
0.9  
HSTL-12  
Class I, II  
VCCIO  
+ 0.3  
0.5 x  
VCCIO  
0.4 x V 0.5 x  
CCIO  
0.6 x  
VCCIO  
VCCIO  
+ 0.48  
1.14  
1.14  
1.2  
1.2  
1.26 0.16  
VCCIO  
0.5 x  
VCCIO  
+0.12  
0.5 x VCCIO 0.5 x  
– 0.12 VCCIO  
0.4 x V 0.5 x  
CCIO  
0.6 x  
VCCIO  
HSUL-12  
1.3 0.26 0.26  
0.44 0.44  
VCCIO  
(1)  
Table 2–19. Differential I/O Standard Specifications for Cyclone V Devices—Preliminary  
(2)  
(2)  
VCCIO (V)  
VID (mV)  
VICM(DC) (V)  
VOD (V)  
VOCM (V)  
I/O Standard  
Min Typ Max Min  
Condition  
Max Min Max  
Min Typ Max Min Typ Max  
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard.  
For transmitter, receiver, and reference clock I/O pin specifications, refer to Table 2–20 on page 2–14.  
PCML  
2.5 V LVDS  
2.375 2.5 2.625 100  
V
V
CM = 1.25 V  
CM = 1.25 V  
0.05 1.8 0.247  
0.3 1.4 0.1  
0.6 1.125 1.25 1.375  
RSDS (HIO) 2.375 2.5 2.625 100  
0.2 0.6  
0.5  
1.2  
1.4  
Mini-LVDS  
2.375 2.5 2.625 200  
(HIO)  
600 0.4 1.325 0.25  
0.6  
1
1.2  
1.4  
LVPECL  
SLVS  
2.375 2.5 2.625 300  
2.375 2.5 2.625 100  
0.6  
1.8  
V
CM = 1.25 V  
0.05 1.8  
Notes to Table 2–19:  
(1) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 2–14.  
(2) RL range: 90 RL 110 Ω  
Power Consumption  
Altera offers two ways to estimate power consumption for a design—the Excel-based  
Early Power Estimator (EPE) and the Quartus® II PowerPlay Power Analyzer feature.  
1
You typically use the interactive Excel-based EPE before designing the FPGA to get a  
magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer  
provides better quality estimates based on the specifics of the design after you  
complete place-and-route. The PowerPlay Power Analyzer can apply a combination  
of user-entered, simulation-derived, and estimated signal activities that, when  
combined with detailed circuit models, yields very accurate power estimates.  
f
For more information about power estimation tools, refer to the PowerPlay Early Power  
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II  
Handbook.  
February 2012 Altera Corporation  
Cyclone V Device Handbook  
Volume 1: Device Overview and Datasheet