1–18
Chapter 1: Overview for Cyclone V Device Family
SoC FPGA with HPS
Features of the HPS
The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of
peripherals, and a shared multiport SDRAM memory controller, as shown in
Figure 1–4.
Figure 1–4. HPS with Dual-Core ARM Cortex-A9 MPCore Processor
Configuration
Controller
Lightweight
HPS-to-FPGA
FPGA Fabric
FPGA-to-HPS HPS-to-FPGA
FPGA-to-HPS SDRAM
FPGA
Manager
HPS
Ethernet
MAC (2x)
ARM Cortex-A9 MPCore
CPU0
(ARM Cortex-A9
with NEON/FPU,
CPU1
(ARM Cortex-A9
with NEON/FPU,
USB
OTG (2x)
64 KB
Boot
ROM
32 KB Instruction Cache, 32 KB Instruction Cache,
32 KB Data Cache, and 32 KB Data Cache, and
Memory Management Unit) Memory Management Unit)
NAND Flash
Controller
Multiport
DDR SDRAM
Controller
with
SD/MMC/SDIO
Controller
Level 3
Interconnect
ACP
SCU
Optional ECC
DMA
Controller
L2 Cache (512 KB)
64 KB
On-Chip
RAM
ETR
(Trace)
Debug
Access Port
Low Speed Peripherals
(Timers, GPIOs, UART, SPI, I2C, CAN, Quad SPI Flash Controller, System Manager, Clock Manager, Reset Manager, and Scan Manager)
System Peripherals
Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC/SDIO
controller module has an integrated DMA controller. For modules without an
integrated DMA controller, an additional DMA controller module provides up to
eight channels of high-bandwidth data transfers. The debug access port provides
interfaces to industry standard JTAG debug probes and supports ARM CoreSight
debug and core traces to facilitate software development.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
