Chapter 1: Overview for Cyclone V Device Family
1–17
Power Management
Instead of using an external flash or ROM, you can configure the Cyclone V devices
through PCIe using CvP. The CvP mode offers the fastest configuration rate and
flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone V CvP
implementation conforms to the PCIe 100 ms power-up-to-active time requirement.
Power Management
Leveraging the FPGA architectural features, process technology advancements, and
transceivers that are designed for power efficiency, the Cyclone V devices consume
less power than previous generation Cyclone FPGAs:
■
Total device core power consumption—less by up to 40%.
Transceiver channel power consumption—less by up to 50%.
■
Additionally, Cyclone V devices contain several hard IP blocks that reduce logic
resources and deliver substantial power savings of up to 25% less power than
equivalent soft implementations.
SoC FPGA with HPS
Each SoC FPGA combines an FPGA fabric and an HPS in a single device. This
combination delivers the flexibility of programmable logic with the power and cost
savings of hard IP in these ways:
■
■
■
Reduces board space, system power, and bill of materials cost by eliminating a
discrete embedded processor
Allows you to differentiate the end product in both hardware and software, and to
support virtually any interface standard
Extends the product life and revenue through in-field hardware and software
updates
February 2012 Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
