Cyclone V Device Overview
CV-51001 | 2018.05.07
Resource
Member Code
D5
84
2
D7
120
2
D9
140
2
Receiver
PCIe Hard IP Block
Hard Memory Controller
2
2
2
Related Information
True LVDS Buffers in Devices, I/O Features in Cyclone V Devices
Provides the number of LVDS channels in each device package.
Package Plan
Table 9.
Package Plan for Cyclone V GT Devices
Transceiver counts shown are for transceiver ≤5 Gbps . 6 Gbps transceiver channel count support depends on
the package and channel usage. For more information about the 6 Gbps transceiver channel count, refer to the
Cyclone V Device Handbook Volume 2: Transceivers.
Member
M301
M383
M484
U484
Code
(11 mm)
(13 mm)
(15 mm)
(19 mm)
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
D5
D7
D9
129
—
4
175
—
6
—
240
—
—
3
224
240
240
6
6
5
—
—
—
—
—
—
—
Member
Code
F484
(23 mm)
F672
(27 mm)
F896
(31 mm)
F1152
(35 mm)
GPIO
240
XCVR
GPIO
336
XCVR
GPIO
—
XCVR
GPIO
—
XCVR
—
D5
D7
D9
6
6
6
6
—
(6)
(6)
240
336
9
480
480
9
—
—
(6)
(7)
(7)
224
336
9
12
560
12
Related Information
6.144-Gbps Support Capability in Cyclone V GT Devices, Cyclone V Device Handbook
Volume 2: Transceivers
Provides more information about 6 Gbps transceiver channel count.
(6)
(7)
If you require CPRI (at 6.144 Gbps) and PCIe Gen2 transmit jitter compliance, Intel
recommends that you use only up to three full-duplex transceiver channels for CPRI, and up to
six full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex
channels.
If you require CPRI (at 6.144 Gbps) and PCIe Gen2 transmit jitter compliance, Intel
recommends that you use only up to three full-duplex transceiver channels for CPRI, and up to
eight full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex
channels.
Cyclone V Device Overview
11
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