Cyclone V Device Overview
CV-51001 | 2018.05.07
External Memory Performance
Table 20.
External Memory Interface Performance in Cyclone V Devices
The maximum and minimum operating frequencies depend on the memory interface standards and the
supported delay-locked loop (DLL) frequency listed in the device datasheet.
Interface
Voltage
(V)
Maximum Frequency (MHz)
Hard Controller Soft Controller
400 303
Minimum Frequency
(MHz)
DDR3 SDRAM
1.5
1.35
1.8
303
303
167
167
400
400
333
303
300
300
DDR2 SDRAM
LPDDR2 SDRAM
1.2
Related Information
External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system
performance specification, use Intel's External Memory Interface Spec Estimator
tool.
HPS External Memory Performance
Table 21.
HPS External Memory Interface Performance
The hard processor system (HPS) is available in Cyclone V SoC devices only.
Interface
Voltage (V)
HPS Hard Controller (MHz)
DDR3 SDRAM
1.5
1.35
1.8
400
400
400
333
DDR2 SDRAM
LPDDR2 SDRAM
1.2
Related Information
External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system
performance specification, use Intel's External Memory Interface Spec Estimator
tool.
Low-Power Serial Transceivers
Cyclone V devices deliver the industry’s lowest power 6.144 Gbps transceivers at an
estimated 88 mW maximum power consumption per channel. Cyclone V transceivers
are designed to be compliant with a wide range of protocols and data rates.
Transceiver Channels
The transceivers are positioned on the left outer edge of the device. The transceiver
channels consist of the physical medium attachment (PMA), physical coding sublayer
(PCS), and clock networks.
Cyclone V Device Overview
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