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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
1-16  
Internal Weak Pull-Up Resistor  
Symbol  
Description  
Maximum  
Unit  
IXCVR-RX (DC)  
DC current per transceiver receiver (RX) pin  
50  
mA  
Internal Weak Pull-Up Resistor  
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.  
Table 1-13: Internal Weak Pull-Up Resistor Values for Arria V Devices  
Symbol  
Description  
Condition (V)(11)  
Value(12)  
25  
Unit  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
VCCIO = 3.3 5%  
VCCIO = 3.0 5%  
VCCIO = 2.5 5%  
VCCIO = 1.8 5%  
VCCIO = 1.5 5%  
VCCIO = 1.35 5%  
VCCIO = 1.25 5%  
VCCIO = 1.2 5%  
25  
25  
Value of the I/O pin pull-up resistor before and during  
configuration, as well as user mode if you have enabled the  
programmable pull-up resistor option.  
25  
RPU  
25  
25  
25  
25  
Related Information  
Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines  
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.  
(10)  
e I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew  
rate.  
(11)  
(12)  
Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO  
.
Valid with 10% tolerances to cover changes over PVT.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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