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5AGXMD3G631I4N 参数 Datasheet PDF下载

5AGXMD3G631I4N图片预览
型号: 5AGXMD3G631I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 1: Overview for the Arria V Device Family  
1–3  
Arria V Feature Summary  
Table 1–1. Feature Summary for Arria V Devices (Part 2 of 3)  
Feature  
Details  
Dual-core ARM Cortex-A9 MPCore processor. Up to 800 MHz maximum frequency that  
supports symmetric and asymmetric multiprocessing  
Interface peripherals—10/100/1000 Ethernet media access control (MAC), USB 2.0 On-  
The-Go (OTG) controller, Quad SPI flash controller, NAND flash controller, and  
SD/MMC/SDIO controller, UART, serial peripheral interface (SPI), I2C interfaces, and up to  
86 GPIO interfaces  
System peripherals—general-purpose and watchdog timers, direct memory access (DMA)  
controller, FPGA configuration manager, and clock and reset managers  
HPS (Arria V SX and ST  
devices only)  
On-chip RAM and boot ROM  
HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-  
FPGA bridges that allow the FPGA fabric to master transactions to slaves in the HPS, and  
vice versa  
FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the  
multiport front end of the HPS SDRAM controller  
ARM CoreSight™ JTAG debug, trace port, and on-chip trace storage  
Three fractional PLLs  
Physical medium  
attachment (PMA) with  
soft PCS  
10GBASE-R  
9.8304-Gbps CPRI  
Enhanced ALM with four registers  
High-performance core  
fabric  
Improved routing architecture to reduce congestion and improve compilation time  
Natively supports three-signal processing precision ranging from 9 x 9, 18 x 19, or 27 x 27  
in the same DSP block  
Variable-precision DSP  
blocks  
64-bit accumulator and cascade for systolic finite impulse responses (FIRs)  
Embedded internal coefficient memory  
Pre-adder/subtractor improves efficiency  
M10K, 10 Kbit with soft error correction code (ECC)  
Memory logic array block (MLAB), 640-bit distributed LUTRAM—you can use up to 25% of  
Internal memory blocks  
the LEs as MLAB memory  
Hardened double data rate3 (DDR3) and DDR2 memory controllers  
Integer mode and fractional mode  
High-resolution Fractional  
PLLs  
Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)  
625-MHz global clock network  
Clock networks  
Global, quadrant, and peripheral clock networks  
Unused clock networks can be powered down to reduce dynamic power  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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