欢迎访问ic37.com |
会员登录 免费注册
发布采购

5AGXMD3G631I4N 参数 Datasheet PDF下载

5AGXMD3G631I4N图片预览
型号: 5AGXMD3G631I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号5AGXMD3G631I4N的Datasheet PDF文件第53页浏览型号5AGXMD3G631I4N的Datasheet PDF文件第54页浏览型号5AGXMD3G631I4N的Datasheet PDF文件第55页浏览型号5AGXMD3G631I4N的Datasheet PDF文件第56页浏览型号5AGXMD3G631I4N的Datasheet PDF文件第58页浏览型号5AGXMD3G631I4N的Datasheet PDF文件第59页浏览型号5AGXMD3G631I4N的Datasheet PDF文件第60页浏览型号5AGXMD3G631I4N的Datasheet PDF文件第61页  
Chapter 2: Device Datasheet for Arria V Devices  
2–29  
Switching Characteristics  
(1)  
Table 2–25. PLL Specifications for Arria V Devices—Preliminary  
(Part 3 of 3)  
Min  
Symbol  
dKBIT  
kVALUE  
fRES  
Parameter  
Bit number of Delta Sigma Modulator (DSM)  
Numerator of Fraction  
Typ  
Max  
TBD (1)  
Unit  
24  
bits  
TBD (1) 8388608  
Resolution of VCO frequency (fINPFD =100 MHz)  
5.96  
Hz  
Notes to Table 2–25:  
(1) Pending silicon characterization.  
(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O  
standard.  
(3) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.  
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.  
(5) FREF is fIN/N when N = 1.  
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404 % confidence level). The output jitter specification applies to  
the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different  
measurement method and are available in Table 2–33 on page 2–35.  
(7) The cascaded PLL specification is only applicable with the following conditions:  
a. Upstream PLL: 0.59 MHz Upstream PLL BW < 1 MHz  
b. Downstream PLL: Downstream PLL BW > 2 MHz  
(8) High bandwidth PLL settings are not supported in external feedback mode.  
(9) External memory interface clock output jitter specifications use a different measurement method, which are available in Table 2–33 on page 2–35.  
DSP Block Specifications  
Table 2–26 lists the Arria V DSP block performance specifications.  
Table 2–26. DSP Block Performance Specifications for Arria V Devices—Preliminary  
Performance  
–C4  
Speed  
Grade  
–C5, I5  
Speed  
Grade  
–C6  
Speed  
Grade  
Mode  
Unit  
Modes using One DSP Block  
Independent 9 x 9 Multiplication  
370  
370  
370  
310  
370  
370  
370  
370  
310  
310  
310  
250  
310  
310  
310  
310  
220  
220  
220  
200  
220  
220  
220  
220  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
Independent 18 x 19 Multiplication  
Independent 18 x 18 Multiplication  
Independent 27 x 27 Multiplication  
Independent 18 x 25 Multiplication  
Independent 20 x 24 Multiplication  
Two 18 x 19 Multiplier Adder Mode  
18 x 18 Multiplier Added Summed with 36-bit Input  
Modes using Two DSP Blocks  
Complex 18 x 19 multiplication  
370  
310  
370  
310  
250  
310  
220  
200  
220  
MHz  
MHz  
MHz  
Two 27 x 27 Multiplier Adder  
Four 18 x 19 Multiplier Adder  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
 复制成功!